A small-area and power-efficient reversible full adder based on a two-transistor multiplexer applicable in image addition - Nature
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AbstractThis study presents an innovative 10-transistor reversible full adder (FA) architecture featuring two garbage outputs (GOs) and no constant inputs (CIs). The design integrates three reversible logic gates across two operational stages, implemented using the gate diffusion input (GDI) methodology. Specifically, it employs two Feynman gates alongside a newly developed GDI-based reversible multiplexer (R-MUX-GDI) to produce the Sum and Carry-out (Cout) signals. The 3 × 3 multiplexer, with two GOs and only two transistors, substantially minimizes the circuit’s footprint. The input configuration is strategically designed to limit excessive GOs. When incorporated into a ripple carry adder (RCA) for image processing, the proposed FA demonstrates exceptional performance in terms of area efficiency, power consumption, and output image quality.
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